參數(shù)資料
型號(hào)： KMPC8270CZUQLDA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 19/83頁(yè)
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II HIP7 480-TBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 333MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 480-LBGA
供應(yīng)商設(shè)備封裝： 408-TBGA（37.5x37.5）
包裝： 托盤
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
26
Freescale Semiconductor
Clock Configuration Modes
7
Clock Configuration Modes
This SoC includes the following clocking modes:
Local
PCI host
PCI agent
The clocking mode is set according to the following input pins as shown in the following table:
PCI_MODE
PCI_CFG[0]
PCI_MODCK
Input hold times
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
—
ns
4, 7
Output valid times
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
—
10
ns
5, 7
5. 7
Output hold times
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
1
—
ns
5, 7
JTAG external clock to output high impedance
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
1
10
ns
5, 6
1 All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
2 The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4 Non-JTAG signal input timing with respect to t
TCLK.
5 Non-JTAG signal output timing with respect to t
TCLK.
6 Guaranteed by design.
7 Guaranteed by design and device characterization.
Table 16. JTAG Timings1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
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KMPC8270CZUUPEA 功能描述:微處理器 - MPU PQ II HIP 7 REV A RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
KMPC8270VRMIBA 功能描述:微處理器 - MPU PQ II HIP 7 REV A VR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
KMPC8270VVUPEA 功能描述:微處理器 - MPU PQ II HIP 7 REV A No PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
KMPC8270ZQMIBA 功能描述:微處理器 - MPU PQ II HIP 7 REV A ZQ RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
KMPC8270ZUUPEA 功能描述:微處理器 - MPU PQ II HIP 7 REV A RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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