參數(shù)資料
型號： KMPC8245LVV333D
廠商： Freescale Semiconductor
文件頁數(shù)： 42/68頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 333MHZ 352-TBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 333MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 352-LBGA
供應(yīng)商設(shè)備封裝： 352-TBGA（35x35）
包裝： 托盤
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
47
System Design
SRESET, TRIG_IN, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240
backward-compatible mode functionality, while a logic 0 state on the SDMA1 signal selects extended
ROM functionality. In extended ROM mode, the TBEN, CHKSTOP_IN, SRESET, TRIG_IN, and
TRIG_OUT functionalities are not available.
The driver names and pin capability of the MPC8245 and the MPC8240 differ slightly. Refer to the drive
capability table (for the ODCR register at 0x73) in the MPC8240 Integrated Processor Hardware
Specifications and Table 4.
The programmable PCI output valid and output hold feature controlled by bits in the power management
configuration register 2 (PMCR2) <0x72> differs slightly in the MPC8245. For the MPC8240, three bits,
PMCR2[6:4] = PCI_HOLD_DEL, are used to select 1 of 8 possible PCI output timing configurations.
PMCR2[6:5] are software-controllable but are initially set by the reset configuration state of the MCP and
CKE signals, respectively. Software can change PMCR2[4]. The default configuration for PMCR2[6:4] =
0b110 since the MCP and CKE signals have internal pull-up resistors, but this default configuration does
not select 33- or 66-MHz PCI operation output timing parameters for the MPC8240. Software makes this
selection. For the MPC8245, only two bits in the power management configuration register 2 (PMCR2),
PMCR2[5:4] = PCI_HOLD_DEL, control the variable PCI output timing. PMCR2[5:4] are software
controllable but are initially set by the inverted reset configuration state of the MCP and CKE signals,
respectively. The default configuration for PMCR2[5:4] = 0b00 since the MCP and CKE signals have
internal pull-up resistors and the values from these signals are inverted; this default configuration selects
66-MHz PCI operation output timing parameters. There are four programmable PCI output timing
configurations on the MPC8245. See Table 11.
Voltage sequencing requirements for the MPC8245 are similar to those for the MPC8240, with two
exceptions in the MPC8245. In the MPC8245, the non-PCI input voltages (Vin) must not be greater than
GVDD or OVDD by more than 0.6 V at all times, including during power-on reset (see Caution 5 in
Table 2). Second, LVDD must not exceed OVDD by more than 3.0 V at any time, including during
power-on reset (see Caution 10 in Table 2); the allowable separation between LVDD and OVDD is 3.6 V
for the MPC8240.
There is no LAVDD input voltage supply signal on the MPC8245 since the SDRAM clock delay-locked
loop (DLL) has power supplied internally. Signal D17 should be treated as a NC for the MPC8245.
Application note AN2128 highlights the differences between the MPC8240 and the MPC8245.
7.7
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all processors that implement the Power Architecture
technology. While the TAP controller can be forced to the reset state using only the TCK and TMS signals,
more reliable power-on reset performance can be obtained if the TRST signal is asserted during power-on
reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP)
function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG, with additional status monitoring signals. The COP port
must independently assert HRESET or TRST to control the processor. If the target system has independent
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