參數(shù)資料
型號: KMPC8241LZQ266D
廠商: Freescale Semiconductor
文件頁數(shù): 57/58頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 266MHZ 357-PBGA
標準包裝: 2
系列: MPC82xx
處理器類型: 32-位 MPC82xx PowerQUICC II
速度: 266MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
8
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 2 shows supply voltage sequencing and separation cautions.
Figure 2. Supply Voltage Sequencing and Separation Cautions
GVDD_OVDD/(LVDD @ 3.3 V - - - -)
VDD/AVDD/AVDD2
LVDD @ 5 V
Time
3.3 V
5 V
2 V
0
3
6
5
6
2
DC
P
o
wer
Suppl
y
V
o
lt
ag
e
Reset
Configuration Pins
HRST_CPU and
HRST_CTRL
PLL
Relock
Time 3
100 s
Nine External Memory
Asserted 255
External Memory
HRST_CPU and
HRST_CTRL
VDD Stable
Power Supply Ramp Up 2
See Note 1
Clock Cycles 3
Clock Cycles Setup Time 4
VM = 1.4 V
One External Memory Clock Cycle 5
Maximum Rise Time Must be Less Than
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.
2. See the Cautions section of Table 2 for details on this topic.
3. Refer to Table 8 for details on PLL relock and reset signal assertion timing requirements.
4. Refer to Table 10 for details on reset configuration pin setup timing requirements.
5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN
clock cycle for the device to be in the nonreset state.
6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation
of HRST_CTRL and HRST_CPU negate in order to be latched.
PLL
6
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