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參數(shù)資料
| 型號： | KMM966G511 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx64 SGRAM SODIMM(512Kx64 圖形RAM模塊) |
| 中文描述： | 512Kx64 SGRAM個SODIMM（512Kx64圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 132K |
| 代理商： | KMM966G511 |
SGRAM MODULE
KMM965G511Q(P)N / KMM966G511Q(P)N
- 2 -
Rev. 2.2 (Jul. 1998)
Revision History
Revision 2.2 (July 1998)
Added -6(166MHz) speed product.
Changed SPD data, Byte #62 from 02h to 00h.
Changed Pin #43 from DQ34 to DQ35 in
PIN CONFIGURATIONS
.
Revision 2.1 (March 1998)
Added KMM965G511 product which does not support SPD.
Added Resistor Strapping Option for 143MHz. in
RESISTOR STRAPPING OPTIONS.
Revision 2.0 (February 1998)
Added KMM966G511-7 product(143MHz @ CL =3).
Removed KMM966G511-H/12 product(-H : 100MHz @ CL =2, -12 : 83MHz @ CL=3).
Changed the Current values of ICC1, ICC4, ICC5, ICC6, ICC7 in
DC CHARACTERISTICS.
Changed tSAC from 6 to 6.5 @ 125MHz, tSS from 2 to 2.5 @ 125MHz in
AC PARAMETER
.
Changed SPD data according to each changed AC Parameters.
Delete a page including
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
Revision 1.2 (December 3, 1997)
Complied with Intel Version 0.9 (December, 1997) specification which is included Updated block diagrams & address
translation table for 512Kx32 devices.
Modified an erratum pin name of Pin #65 from CS1 to CS1, Pin #66 from CS0 to CS0, Pin #94 from ADD to VDD in
PIN
CONFIGURATIONS
- page 3.
Revision 1.1 (November 18, 1997)
Changed the name of Pin #80 from BA(A10) to A8, Pin #81 from A9 to BA(A10), Pin #82 from A8 to A9/AP in
PIN CON
FIGURATIONS
.
Revision 1.0 (November 13, 1997)
Initial Draft --- Preliminary Spec. (comply with Intel 0.2 spec. which is basically compatible with Intel 0.1 spec. except the
changed functionality of
Strapping Resistor
DQ31 from Memory Timing to CAS Latency.
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