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參數(shù)資料
| 型號： | KMC850DSLCZQ50BU |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC CPM 50MHZ 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（23x23） |
| 包裝： | 托盤 |
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MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
10
Freescale Semiconductor
Bus Signal Timing
θ
JA
= Package thermal resistance, junction to ambient,
°C/W
P
D
= P
INT
+ P
I/O
P
INT
= I
DD
x V
DD
,
watts—chip internal power
P
I/O
= Power dissipation on input and output pins—user determined
For most applications P
I/O
< 0.3 P
INT
and can be neglected. If P
I/O
is neglected, an approximate
relationship between P
D
and T
J
is:
P
D
= K
÷ (T
J
+ 273
°C)(2)
Solving equations (1) and (2) for K gives:
K = P
D
(T
A
+ 273
°C) + θ
JA
P
D
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
P
D
(at equilibrium) for a known T
A
. Using this value of K, the values of P
D
and T
J
can be obtained by
solving equations (1) and (2) iteratively for any value of T
A
.
5.1
Layout Practices
Each V
CC pin on the MPC850 should be provided with a low-impedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four
0.1 F by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.
All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data busses. Maximum PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
6
Bus Signal Timing
Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing
information for other bus speeds can be interpolated by equation using the MPC850 Electrical
Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10
pF. Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.
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