參數(shù)資料
型號(hào)： KMC7457RX1000NC
廠商： Freescale Semiconductor
文件頁數(shù)： 53/71頁
文件大?。?/td> 0K
描述： IC MPU RISC 32BIT 1000MHZ 483BGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 1.0GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 483-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 483-FCCBGA（29x29）
包裝： 托盤
System Design Information
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
57
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
The L3 interface does not normally require pull-up resistors. Unused L3_ADDR signals are driven low
when the SRAM is configured to be less than 1 M in size via L3CR. For example, L3_ADD[18] will be
driven low if the SRAM size is configured to be 2 M; likewise, L3_ADDR[18:17] will be driven low if
the SRAM size is configured to be 1 M.
9.7
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, the COP reset signals must be merged
into these signals with logic.
The arrangement shown in Figure 26 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
power-on. While Freescale recommends that the COP header be designed into the system as shown in
Figure 26, if this is not possible, the isolation resistor will allow future access to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in Figure 26 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 26; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 26 is common to all known emulators.
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