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參數(shù)資料
| 型號(hào)： | KMC68LC302AF20CT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 20MHZ 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 20MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
MC68LC302 PRODUCT INFORMATION
FEATURES
The features of the MC68LC302 are as follows. Bold face items show major differences from the MC68302.
On-Chip Static 68000 Core Supporting a 16- or 8-Bit M68000 Family System
SIB Including:
— Independent Direct Memory Access (IDMA) Controller
— Interrupt Controller with Two Modes of Operation
— Parallel Input/Output (I/O) Ports, Some with Interrupt Capability
— On-Chip 1152-Byte Dual-Port RAM
— Three Timers Including a Watchdog Timer
— New Periodic Interrupt Timer (PIT)
— Four Programmable Chip-Select Lines with Wait-State Generator Logic
— Programmable Address Mapping of the Dual-Port RAM and IMP Registers
— On-Chip Clock Generator with Output Signal
— On-Chip PLL Allows Operation with 32 kHz or 4 MHz Crystals
— Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM
— Allows Boot in 8-bit Mode, and Running Switch to 16-bit Mode
— System Control:
System Status and Control Logic
Disable CPU Logic (Slave Mode Operation)
Hardware Watchdog
New Low-Power (Standby) Modes with Wake-Up from Two Pins or PIT
Freeze Control for Debugging (Available Only in the PGA Package)
DRAM Refresh Controller
CP Including:
— Main Controller (RISC Processor)
— Two Independent Full-Duplex Serial Communications Controllers (SCCs)
— Supporting Various Protocols:
High-Level/Synchronous Data Link Control (HDLC/SDLC)
Universal Asynchronous Receiver Transmitter (UART)
Binary Synchronous Communication (BISYNC)
Transparent Modes
Autobaud Support
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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