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參數(shù)資料
| 型號： | KM68V1000BLRE-7 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 183K |
| 代理商： | KM68V1000BLRE-7 |
KM68V1000B, KM68U1000B Family
CMOS SRAM
Revision 2.0
March 1998
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
3.0/2.7V
1)
2.2V
V
DR
CS
1
GND
Data Retention Mode
CS
1
≥
V
CC
- 0.2V
t
SDR
t
RDR
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
1
Controlled)
Address
CS
1
t
AW
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR(1)
applied in case a write ends as CS
1
or WE going high t
WR(2)
applied in case a write ends as CS
2
going to low.
CS
2
t
CW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(2)
t
WR(4)
t
WP(1)
t
DW
t
DH
t
AS(3)
t
WC
CS
2
controlled
V
CC
3.0/2.7V
1)
CS
2
0.4V
GND
V
DR
Data Retention Mode
t
SDR
t
RDR
1. 3.0V for KM68V1000B Family , 2.7V for KM68U1000B Family
CS
2
≤
0.2V
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