參數(shù)資料
型號: KM68U4000C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x8 bit Low Power and Low Voltage CMOS Static RAM(512K x8位低功耗低電壓CMOS 靜態(tài) RAM)
中文描述: 為512k x8位低功耗和低電壓的CMOS靜態(tài)RAM(為512k x8位低功耗低電壓的CMOS靜態(tài)RAM)的
文件頁數(shù): 6/10頁
文件大小: 174K
代理商: KM68U4000C
KM68V4000C, KM68U4000C Family
Preliminary
CMOS SRAM
Revision 0.1
June 1998
6
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
Address
OE
Data out
NOTES
(READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ
t
RC
t
OE
t
CO1
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