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參數(shù)資料
| 型號： | KM68512ALT-7L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx8 bit Low Power CMOS Static RAM |
| 中文描述： | 64Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 143K |
| 代理商： | KM68512ALT-7L |
KM68512A Family
CMOS SRAM
Revision 4.0
January 1997
5
AC CHARACTERISTICS
(Vcc=4.5~5.5V, KM68512A Family:T
A
=0 to 70
°
C, KM68512AI Family:T
A
=-40 to 85
°
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO1
, t
CO2
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
25
ns
Output disable to high-Z output
t
OHZ
0
20
0
25
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
DATA RETENTION CHARACTERISTICS
1.
CS
1
≥
Vcc-0.2V, CS
2
≥
Vcc-0.2V( CS
1
controlled) or CS
2
≤
0.2V(CS
2
controlled).
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
1)
≥
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
KM68512AL/L-L
Vcc=3.0V CS
1
≥
Vcc-0.2V
CS
2
≥
Vcc-0.2V or CS
2
≤
0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
-
-
-
-
0
1
0.5
-
-
-
50
10
50
25
-
μ
A
KM68512ALI/LI-L
Data retention set-up time
t
SDR
See data retention waveform
ms
Recovery time
t
RDR
5
-
-
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