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參數(shù)資料
| 型號： | KM681001B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x 8 Bit High-Speed CMOS Static RAM |
| 中文描述： | 128K的× 8位高速CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 181K |
| 代理商： | KM681001B |
KM681001B
CMOS SRAM
PRELIMINARY
Rev 2.0
- 8 -
February 1998
FUNCTIONAL DESCRIPTION
* NOTE : X means Don
′
t Care.
CS
1
CS
2
WE
OE
Mode
I/O Pin
Supply Current
H
X
X
X*
Not Select
High-Z
I
SB
, I
SB1
X
L
X
X
Not Select
High-Z
I
SB
, I
SB1
L
H
H
H
Output Disable
High-Z
I
CC
L
H
H
L
Read
D
OUT
I
CC
L
H
L
X
Write
D
IN
I
CC
NOTES
(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition CS
1
going low,
CS
2
going high and WE going low ; A write ends at the earliest transition CS
1
going high or CS
2
going low or WE going high.
t
WP
is measured from the beginning of write to the end of write.
3. t
CW
is measured from the later of CS
1
going low or CS
2
going high to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR1
applied in case a write ends as CS
1
or WE going high. t
WR2
applied in case a write ends as CS
2
going low.
6. If OE, CS
1
, CS
2
and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS
1
goes low and CS
2
goes high simultaneously with WE going or after WE going low, the outputs remain high impedance
state.
9. Dout is the read data of the new address.
10.When CS
1
is low and CS
2
is high : I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
TIMING WAVEFORM OF WRITE CYCLE(4)
(CS
2
= Controlled)
Address
CS
1
t
AS(4)
CS
2
t
WP(2)
WE
Data in
Valid Data
Data out
High-Z
High-Z
t
CW(3)
t
DW
t
DH
t
WC
t
WR(5)
t
AW
t
WHZ(6)
t
LZ
相關PDF資料 |
PDF描述 |
|---|---|
| KM681001B-15 | 128K x 8 Bit High-Speed CMOS Static RAM |
| KM681001BLJ-15 | x8 SRAM |
| KM681001BLJ-17 | x8 SRAM |
| KM681001BLJ-20 | x8 SRAM |
| KM681001BLJI-15 | x8 SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KM681001B-15 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K x 8 Bit High-Speed CMOS Static RAM |
| KM681001B-20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K x 8 Bit High-Speed CMOS Static RAM |
| KM681001BJ-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| KM681001BJ-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| KM681001BJ-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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