
KM681001B
CMOS SRAM
PRELIMINARY
Rev 2.0
- 2 -
February 1998
128K x 8 Bit High-Speed CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
Fast Access Time 15, 20ns(Max.)
Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating KM681001B - 15 : 125mA(Max.)
KM681001B - 20 : 123mA(Max.)
Single 5.0V
±
10% Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Standard Pin Configuration
KM681001BJ : 32-SOJ-400
KM681001BSJ : 32-SOJ-300
Clk Gen.
I/O
1
~ I/O
8
CS
1
WE
OE
FUNCTIONAL BLOCK DIAGRAM
R
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
256x8 Columns
I/O Circuit
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
16
Address Inputs
WE
Write Enable
CS
1
, CS
2
Chip Selects
OE
Output Enable
I/O
1
~ I/O
8
Data Inputs/Outputs
V
CC
Power(+5.0V)
V
SS
Ground
N.C
No Connection
The KM681001B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681001B uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung
′
s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681001B is packaged
in a 400/300 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A
16
CS
2
WE
A
15
A
14
A
13
A
12
OE
A
11
CS
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
N.C
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
I/O
2
I/O
3
Vss
CS
2
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8