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參數(shù)資料
| 型號： | KM6264BLP-7L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8Kx8 bit Low Power CMOS Static RAM |
| 中文描述： | 8Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 152K |
| 代理商： | KM6264BLP-7L |
KM6264B Family
ELECTRONICS
CMOS SRAM
Revision. 0.0
Auust. 1996
9
FUNCTIONAL DESCRIPTION
/CS1
H
X
L
L
L
/WE
X
X
H
H
L
Mode
Power Down
Power Down
Output Disable
Read
Write
Current Mode
Isb, Isb1
Isb, Isb1
Icc
Icc
Icc
I/O Pin
High-Z
High-Z
High-Z
Dout
Din
/OE
X
X
H
L
X
CS2
X
L
H
H
H
Notes(Write Cycle)
1. A write occurs during the overlap of a low /CS1, a high CS2 and a low /WE. A write begins at the latest transition
among /CS1 going low, CS2 going high and /WE going low. A write ends at the earliest transition among /CS1 going
high, CS2 going low and /WE going high, tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at /CS1, or /WE
going high, tWR2 applied in case a write ends at CS2 going to low.
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS2 Controlled)
t
WC
t
CW(2)
t
WR2(4)
t
AW
t
WP(1)
Address
/CS1
/WE
Data in
Data out
t
DW
Data Vailid
t
AS(3)
High - Z
High - Z
DH
t
CS2
t
CW(2)
* X means don't care
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