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參數(shù)資料
| 型號： | KM6264BLP-12L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8Kx8 bit Low Power CMOS Static RAM |
| 中文描述： | 8Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 152K |
| 代理商： | KM6264BLP-12L |
KM6264B Family
ELECTRONICS
CMOS SRAM
Revision. 0.0
Auust. 1996
7
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (1)
(Address Controlled)
(/CS=/OE=Vil, CS2=/WE=Vih)
Address
Data Out
t
RC
Previous Data Valid
Data Valid
t
AA
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(/WE= V
IH
)
t
RC
t
AA
t
CO1
t
OE
t
OLZ
t
OH
t
LZ
t
OHZ
Address
/CS1
/OE
Data out
Data Vailid
High - Z
Notes(Read Cycle)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max) is less than tLZ(Min) both for a given device and
device to device interconnection.
t
CO2
CS2
t
HZ
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