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參數(shù)資料
| 型號(hào)： | KM62256DLRG-7L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx8 bit Low Power CMOS Static RAM |
| 中文描述： | 32Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大小： | 170K |
| 代理商： | KM62256DLRG-7L |
KM62256D Family
CMOS SRAM
Revision 1.0
November 1997
RECOMMENDED DC OPERATING CONDITIONS
1)
Note:
1. Commercial Product : T
A
=0 to 70
°
C, otherwise specified
Industrial Product : T
A
=-40 to 85
°
C, otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width
≤
30ns
3. Undershoot : -3.0V in case of pulse width
≤
30ns
4. Overshoot and undershoot are sampled, not 100% tested
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.5V
2)
V
Input low voltage
V
IL
-0.5
3)
-
0.8
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
°
C)
1. Capacitance is sampled not, 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
μ
A
μ
A
Output leakage current
I
LO
CS=V
IH
or OE=V
IH
or WE=V
IL
, V
IO
=V
SS
to Vcc
-1
-
1
Operating power supply current
I
CC
I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
, Read
-
5
10
mA
Average operating current
I
CC1
Cycle time=1
μ
s, 100% duty, I
IO
=0mA
CS
≤
0.2V, V
IN
≤
0.2V, V
IN
≥
Vcc -0.2V
Read
-
2
5
mA
Write
-
20
I
CC2
Cycle time=Min,100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
-
45
60
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS=V
IH
, Other inputs=V
IH
or V
IL
-
-
1
mA
Standby Current (CMOS)
I
SB1
CS
≥
Vcc-0.2V, Other inputs=0~Vcc
Low Power
-
1
30
μ
A
μ
A
Low Low Power
-
0.2
5
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