參數(shù)資料
型號: KM62256CLTGI-7
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 32Kx8 bit Low Power CMOS Static RAM
中文描述: 32Kx8位低功耗CMOS靜態(tài)RAM
文件頁數(shù): 5/10頁
文件大?。?/td> 162K
代理商: KM62256CLTGI-7
PRELIMINARY
CMOS SRAM
Revision 3.0
April 1996
KM62256C Family
TEST CONDITIONS
(2. Temperature and Vcc Conditions)
* The parameter is measured with 30pF test load
Product Family
Temperature
Power Supply(Vcc)
Speed Bin
Comments
KM62256CL/L-L
0~70
é
5V
10%
45*/55/70ns
Commercial
KM62256CLE/LE-L
-25~85
é
5V
10%
70/100ns
Extended
KM62256CLI/LI-L
-40~85
é
5V
10%
70/100ns
Industrial
PARAMETER LIST FOR EACH SPEED BIN
* The parameter is measured with 30pF test load
Parameter List
Symbol
Speed Bins
Units
45ns*
55ns
70ns
100ns
Min
Max
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
45
-
55
-
70
-
100
-
ns
Address access time
-
45
-
55
-
70
-
100
ns
Chip select to output
-
45
-
55
-
70
-
100
ns
Output enable to valid output
-
25
-
25
-
35
-
50
ns
Chip select to low-Z output
10
-
10
-
10
-
10
-
ns
Output enable to low-Z output
5
-
5
-
5
-
5
-
ns
Chip disable to high-Z output
0
20
0
20
0
30
0
35
ns
Output disable to high-Z output
0
20
0
20
0
30
0
35
ns
Output hold from address change
5
-
5
-
5
-
5
-
ns
Write
Write cycle time
45
-
55
-
70
-
100
-
ns
Chip select to end of write
45
-
45
-
60
-
80
-
ns
Address set-up time
0
-
0
-
0
-
0
-
ns
Address valid to end of write
45
-
45
-
60
-
80
-
ns
Write pulse width
40
-
40
-
50
-
60
-
ns
Write recovery time
0
-
0
-
0
-
0
-
ns
Write to output high-Z
0
20
0
20
0
25
0
35
ns
Data to write time overlap
25
-
25
-
30
-
50
-
ns
Data hold from write time
0
-
0
-
0
-
0
-
ns
End write to output low-Z
5
-
5
-
5
-
5
-
ns
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