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參數(shù)資料
| 型號： | KM62256CLTG-4L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx8 bit Low Power CMOS Static RAM |
| 中文描述： | 32Kx8位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 162K |
| 代理商： | KM62256CLTG-4L |
PRELIMINARY
CMOS SRAM
Revision 3.0
April 1996
KM62256C Family
TIMING WAVEFORM OF WRITE CYCLE(1)
TIMING WAVEFORM OF WRITE CYCLE(2)
Address
CS
Data Valid
WE
Data in
High-Z
High-Z
Address
CS
Data Undefined
Data Valid
WE
Data in
Data out
Data out
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap(
t
WP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE going low : A write end
at the earliest transition among CS going high and WE going high,
t
WP is measured from the beginning of write to the end of write.
2.
t
CW is measured from the CS going low to end of write.
3.
t
AS is measured from the address valid to the beginning of write.
4.
t
WR is measured from the end of write to the address change.
t
WR applied in case a write ends as CS or WE going high.
t
WR(4)
t
CW(2)
t
AW
t
WP(1)
t
AS(3)
t
DW
t
DH
t
OW
t
WHZ
t
WC
t
WR(4)
t
CW(2)
t
WP(1)
t
DW
t
DH
t
AW
t
AS(3)
t
WC
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| KM62256CLTG-5 | 32Kx8 bit Low Power CMOS Static RAM |
| KM62256CLTG-5L | 32Kx8 bit Low Power CMOS Static RAM |
| KM62256CLTG-7 | 32Kx8 bit Low Power CMOS Static RAM |
| KM62256CLTG-7L | 32Kx8 bit Low Power CMOS Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM62256CLTG-5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Kx8 bit Low Power CMOS Static RAM |
| KM62256CLTG5L | 制造商:SAMSUNG 功能描述:* |
| KM62256CLTG-5L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Kx8 bit Low Power CMOS Static RAM |
| KM62256CLTG-7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32Kx8 bit Low Power CMOS Static RAM |
| KM62256CLTG-7L | 制造商:Samsung Semiconductor 功能描述: |
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