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參數(shù)資料
| 型號： | KM6164002A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx16 bit Low Power CMOS Static RAM(256Kx16位低功耗CMOS 靜態(tài) RAM) |
| 中文描述： | 256Kx16位低功耗CMOS靜態(tài)RAM（256Kx16位低功耗的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 132K |
| 代理商： | KM6164002A |
KM6164002A, KM6164002AE, KM6164002AI
CMOS SRAM
PRELIMINARY
Rev 2.0
- 8 -
February 1998
FUNCTIONAL DESCRIPTION
* NOTE : X means Don
′
t Care.
CS
WE
OE
LB
UB
Mode
I/O Pin
Supply Current
I/O
1
~I/O
8
I/O
9
~I/O
16
H
X
X*
X
X
Not Select
High-Z
High-Z
I
SB
, I
SB1
L
H
H
X
X
Output Disable
High-Z
High-Z
I
CC
L
X
X
H
H
L
H
L
L
H
Read
D
OUT
High-Z
I
CC
H
L
High-Z
D
OUT
L
L
D
OUT
D
OUT
L
L
X
L
H
Write
D
IN
High-Z
I
CC
H
L
High-Z
D
IN
L
L
D
IN
D
IN
Address
CS
Valid Data
UB, LB
WE
Data in
Data out
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
t
WC
t
CW(3)
t
BW
t
WP(2)
t
DH
t
DW
t
WR(5)
t
AW
t
AS(4)
High-Z
High-Z(8)
t
BLZ
t
WHZ(6)
High-Z
NOTES
(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE
going low ; A write ends at the earliest transition CS going high or WE going high. t
WP
is measured from the beginning of write
to the end of write.
3. t
CW
is measured from the later of CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
相關(guān)PDF資料 |
PDF描述 |
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| KM6164002AE | 256Kx16 bit Low Power CMOS Static RAM(256Kx16位低功耗CMOS 靜態(tài) RAM) |
| KM6164002AI | 256Kx16 bit Low Power CMOS Static RAM(256Kx16位低功耗CMOS 靜態(tài) RAM) |
| KM6164002B | 256K x 16 Bit High-Speed CMOS Static RAM(256Kx16位低功耗CMOS 靜態(tài) RAM) |
| KM6164002BI | 256K x 16 Bit High-Speed CMOS Static RAM(256Kx16位低功耗CMOS 靜態(tài) RAM) |
| KM6164002 | CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM6164002AJ-20 | 制造商:SEC 功能描述: |
| KM6164002E | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
| KM6164002I | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
| KM6164002J-20 FAB | 制造商:Samsung Semiconductor 功能描述: |
| KM616B4002J-12 | 制造商:SEC 功能描述: |
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