參數(shù)資料
型號: KM611001
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x 1Bit High-Speed CMOS SRAM
中文描述: 100萬x 1位高速CMOS SRAM的
文件頁數(shù): 1/8頁
文件大?。?/td> 95K
代理商: KM611001
KM611001/L
CMOS SRAM
Rev 2.0
July-1996
1
Fast Access Time 20, 25, 35ns(Max.)
Low Power Dissipation
Standby (TTL) : 40 mA(Max.)
(CMOS): 2 mA(Max.)
0.5 mA(Max.) - L-ver.
OperatingKM611001/L -20 : 130 mA(Max.)
KM611001/L -25 : 110 mA(Max.)
KM611001/L -35 : 100 mA(Max.)
Single 5.0V ± 10% Power Supply
TTL Compatible Inputs and Outputs
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Low Data Retention Voltage : 2V(Min.)- L-Ver Only
Standard Pin Configuration
KM611001P/LP : 28-DIP-400
KM611001J/LJ : 28-SOJ-400A
The KM611001/L is a 1,048,576-bit high-speed Static
Random Access Memory organized as 1,048,576
words by 1 bit. The KM611001/L has separate input
and output lines for fast read and write access. The
device is fabricated using Samsung`s advanced
CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-
density
high-speed
system
KM611001/L is packaged in a 400 mil 28-pin plastic DIP
or SOJ.
applications.
The
1M x 1Bit High-Speed CMOS SRAM
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
Address Inputs
Write Enable
Chip Select
Data Input
Data Output
Power (+5V)
Ground
No Connection
Pin Name
A0-A19
/WE
/CS
DIN
DOUT
Vcc
Vss
N.C
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SOJ/DIP
A0
A1
A2
A3
A4
A5
N.C
A6
A7
A8
A9
DOUT
/WE
Vss
Vcc
A19
A18
A17
A16
A15
A14
N.C
A13
A12
A11
A10
DIN
/CS
PIN DESCRIPTION
GENERAL DESCRIPTION
A0
A1
A2
A3
A5
A6
A7
A8
A9
DIN
MEMORY ARRAY
512 Rows
2048x1 Columns
Pre-Charge Circuit
R
Data
Cont.
A4 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
/CS
/WE
I/O Circuit
Column Select
Clk Gen.
Clk
Gen.
DOUT
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