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參數(shù)資料
| 型號(hào)： | KM48S32230A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8M x 8Bit x 4 Banks Synchronous DRAM(8M x 8位 x 4組同步動(dòng)態(tài)RAM) |
| 中文描述： | 8米× 8位× 4銀行同步DRAM（8米× 8位× 4組同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 62K |
| 代理商： | KM48S32230A |
KM48S32230A
CMOS SDRAM
REV. 0 May '98
Preliminary
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-8
-H
-L
-10
Row active to row active delay
t
RRD
(min)
16
20
20
20
ns
1
RAS to CAS delay
t
RCD
(min)
20
20
20
24
ns
1
Row precharge time
t
RP
(min)
20
20
20
24
ns
1
Row active time
t
RAS
(min)
48
50
50
50
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
68
70
70
80
ns
1
Last data in to row precharge
t
RDL
(min)
8
10
10
12
ns
2
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Notes :
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