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參數(shù)資料
| 型號(hào)： | KM48S16030A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 128Mbit SDRAM的4米× 8位× 4銀行同步DRAM LVTTL |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | KM48S16030A |
KM48S16030A
CMOS SDRAM
Rev. 0.1 Jun. 1999
Revision History
Revision 0.0 (May 15, 1999)
Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
Skip ICC4 value of CL=2 in DC characteristics in datasheet.
Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
Symbol Change Notice
Revision 0.1 (Jun 28, 1999)
Added Notes @OPERATING AC PARAMETER
Notes : 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommands tRDL=2CLK and tDAL=2CLK + 20ns.
Added -10 bining product.
Before
After
I
IL
I
IL
I
OL
Input leakage current (inputs)
Input leakage current (I/O pins)
Output open @ DC characteristic table
I
LI
Input leakage current
I
o
Output open @ DC characteristic table
Test Condition in
DC CHARACTERISTIC Change Notice
Symbol
Before
After
I
CC2P ,
I
CC3P
I
CC2N ,
I
CC3N
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
2 Banks activated
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
4 Banks activated
I
CC4
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| KM48S16030AT-G/F10 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| KM48S16030AT-G/F8 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| KM48S16030AT-G/FA | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| KM48S16030AT-G/FH | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| KM48S16030AT-G/FL | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
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