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參數(shù)資料
| 型號： | KM418RD2AC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 24.9K 1% 1/4W -200 TO +500 PPM/C MF |
| 中文描述： | 128/144Mbit RDRAM的256 × 16/18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數(shù)： | 48/64頁 |
| 文件大?。?/td> | 4052K |
| 代理商： | KM418RD2AC |
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Page 45
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
t
DR1,
t
DF1
SIO0, SIO1 input rise and fall times
-
5.0
ns
Figure 56
t
DR2,
t
DF2
CMD, SCK input rise and fall times
-
2.0
ns
Figure 56
t
CYCLE1
SCK cycle time - Serial control register transactions
1000
-
ns
Figure 56
SCK cycle time - Power transitions
10
-
ns
Figure 56
t
CH1
, t
CL1
SCK high and low times
4.25
-
ns
Figure 56
t
S1
CMD setup time to SCK rising or falling edge
e
1
-
ns
Figure 56
t
H1
CMD hold time to SCK rising or falling edge
e
1
-
ns
Figure 56
t
S2
SIO0 setup time to SCK falling edge
40
-
ns
Figure 56
t
H2
SIO0 hold time to SCK falling edge
40
-
ns
Figure 56
t
S3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 48,
Figure 57
t
H3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
t
S4
ROW2..0, COL4..0 setup time for quiet window
-1
-
t
CYCLE
Figure 48
t
H4
ROW2..0, COL4..0 hold time for quiet window
f
5
-
t
CYCLE
Figure 48
v
IL,CMOS
CMOS input low voltage - over/undershoot voltage duration is less
than or equal to 5ns
- 0.7
V
CMOS
/2
- 0.6
V
v
IH,CMOS
CMOS input high voltage - over/undershoot voltage duration is less
than or equal to 5ns
V
CMOS
/2
+ 0.6
V
CMOS
+
0.7
V
t
NPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
t
CYCLE
Figure 47
t
READTOCC
Offset between read data and CC packets (same device)
12
-
t
CYCLE
Figure 51
t
CCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
t
CYCLE
Figure 51
t
CE
CTM/CFM stable before NAP/PDN exit
2
-
t
CYCLE
Figure 48
t
CD
CTM/CFM stable after NAP/PDN entry
100
-
t
CYCLE
Figure 47
t
FRM
ROW packet to COL packet ATTN framing delay
7
-
t
CYCLE
Figure 46
t
NLIMIT
Maximum time in NAP mode
10.0
μ
s
Figure 45
t
REF
Refresh interval
32
ms
Figure 50
t
CCTRL
Current control interval
34 t
CYCLE
100ms
ms/t
CYCLE
Figure 51
t
TEMP
Temperature control interval
100
ms
Figure 52
t
TCEN
TCE command to TCAL command
150
-
t
CYCLE
Figure 52
t
TCAL
TCAL command to quiet window
2
2
t
CYCLE
Figure 52
t
TCQUIET
Quiet window (no read data)
140
-
t
CYCLE
Figure 52
t
PAUSE
RDRAM delay (no RSL operations allowed)
200.0
μ
s
page 28
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with t
CYCLE
=3.33ns.
c. This parameter also applies to a -800 part when operated with t
CYCLE
=2.81ns.
d. t
S,MIN
and t
H,MIN
for other t
CYCLE
values can be interpolated between or extrapolated from the timings at the 3 specified t
CYCLE
values.
e. With V
IL,CMOS
=0.5V
CMOS
-0.6V and V
IH,CMOS
=0.5V
CMOS
+0.6V
f. Effective hold becomes t
H4
’
=
t
H4
+[PDNXA
64
t
SCYCLE
+t
PDNXB,MAX
]-[PDNX
256
t
SCYCLE
]
if [PDNX
256
t
SCYCLE
] < [PDNXA
64
t
SCYCLE
+t
PDNXB,MAX
]. See Figure 48.
Table 19: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
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相關(guān)代理商/技術(shù)參數(shù) |
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| KM418RD2AD | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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| KM418RD2D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32AD | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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