參數(shù)資料
型號： KM416V4004C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4M x 16bit CMOS Dynamic RAM with Extended Data Out(4M x 16位 CMOS動態(tài)RAM(帶擴展數(shù)據(jù)輸出))
中文描述： 4米× 16位的擴展數(shù)據(jù)輸出的CMOS動態(tài)RAM（4米× 16位的CMOS動態(tài)隨機存儲器（帶擴展數(shù)據(jù)輸出））
文件頁數(shù)： 8/36頁
文件大小： 732K
代理商： KM416V4004C
KM416V4004C,KM416V4104C
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition
times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If
t
WCS
≥
t
WCS
(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min) and
t
AWD
≥
t
AWD
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifiecations are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
ASC
,
t
CAH
are referenced to the earlier CAS falling edge.
t
CP
is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
t
CWD
is referenced to the later CAS falling edge at word read-modify-write cycle.
KM416V40(1)04C Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
7.
6.
5.
10.
9.
8.
13.
12.
11.
15.
14.
3.
2.
1.
4.
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