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參數(shù)資料
| 型號(hào)： | KM23V4100DT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M-Bit (512Kx8 /256x16) CMOS Mask ROM(4M位(512Kx8 /256x16) CMOS掩膜ROM) |
| 中文描述： | 4分位（512Kx8 / 256x16）的CMOS掩模ROM（4分位（512Kx8 / 256x16）的CMOS掩膜光盤(pán)） |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 60K |
| 代理商： | KM23V4100DT |
KM23V4100D(E)T
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
°
C to +70
°
C, V
CC
=3.3V/3.0V
±
0.3V, unless otherwise noted.)
READ CYCLE
Item
Symbol
V
CC
=3.3V
±
0.3V
V
CC
=3.0V
±
0.3V
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
100
120
ns
Chip Enable Access Time
t
ACE
100
120
ns
Address Access Time
t
AA
100
120
ns
Output Enable Access Time
t
OE
50
60
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
ns
Output Hold from Address Change
t
OH
0
0
ns
TIMING DIAGRAM
READ
ADD
A
0
~A
17
A
-1(*1)
CE/CE
OE/OE
D
OUT
D
0
~D
7
D
8
~D
15(*2)
ADD1
ADD2
VALID DATA
VALID DATA
t
OH
t
DF(*3)
t
RC
t
ACE
t
OE
t
OE
NOTES :
*1. Byte Mode only. A
-1
is Least Significant Bit Address.(BHE = V
IL
)
*2. Word Mode only.(BHE = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
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