參數(shù)資料
型號: KK74LV164N
廠商: KODENSHI CORP.
英文描述: 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
中文描述: 8位SERIAL-IN/PARALLEL-OUT移位寄存器
文件頁數(shù): 1/6頁
文件大?。?/td> 205K
代理商: KK74LV164N
TECHNICAL DATA
8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
K K
74LV164
The
KK
74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the
KK
74HC/HCT164.
The
KK
74LV164 is an 8-bit edge-triggered shift register with serial
data entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (DSA or DSB); either input can be used
as an active HIGH enable for data entry through the other input. Both
inputs must be connected together or an unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q
0
, which is the logical AND of the
two data inputs (DSA, DSB ) that existed one set-up time prior to the rising
clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 1.2 to 5.5 V
Low Input Current: 1.0
μ
A, 0.1
μ
А
at
Т
= 25
°
С
Output Current: 6 mA at V
CC
= 3.0 V; 12 mA at V
CC
= 4.5 V
High Noise Immunity Characteristic of CMOS Devices
1
14
1
14
N SUFFIX
PLASTIC DIP
D SUFFIX
SO
ORDERING INFORMATION
K K
74LV164N
Plastic
K K
74LV164D
SOIC
T
A
= -40
°
to 125
°
C for all packages
LOGIC DIAGRAM
PIN 14=V
CC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
CP
Outputs
Q0 Q1 ... Q7
MR
DSA
DSB
L
X
X
X
L
L … L
H
L
L
L
Q0 ... Q6
H
L
H
L
Q0 ... Q6
H
H
L
L
Q0 ... Q6
H
H
H
H
Q0 ... Q6
H = high voltage level
L = low voltage level
X = don’t care
DSA
DSB
CP
SERIAL
DATA
INPUTS
PARALLEL
DATA
OUTPUTS
MR
Q0
Q4
Q2
Q6
Q1
Q5
Q3
Q7
1
2
8
9
2
10
5
12
4
11
6
13
DATA
1
2
3
5
4
6
7
V
CC
Q7
14
13
12
11
10
8
9
GND
DSA
DSB
Q0
Q1
Q2
Q3
Q6
Q5
Q4
MR
CP
1
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