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參數(shù)資料
| 型號(hào)： | KG |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Dual Mode CDMA/AMPS Baseband Interface |
| 中文描述： | 雙模式CDMA / AMPS二元基帶接口 |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大小： | 153K |
| 代理商： | KG |
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The PLUTO baseband interface circuit is designed for use
in dual mode CDMA/AMPS digital cellular telephones. In the
telephone, Pluto provides the interface between the radio (RF
& IF) components and the baseband digital signal processor.
Pluto is part of a complete chipset solution for CDMA phones
entitled the Planet chipset.
The receive (RX) section converts the analog in-phase and
quadrature (I & Q) signals into equivalent digital signals whilst
the transmit (TX) circuits perform the complementary function
of translating digital baseband information into the analog
equivalent signals required for the modulator in the radio
circuits. VHF PLLS are also included for second RXLO and
TXIF generation.
PLUTO also contains a 4 channel general purpose ADC
which is included for such purposes as environmental and
signal strength monitoring.
FEATURES
I
Dual mode AMPS/CDMA compatible
I
Low Power/Low Voltage operation
I
Standard baseband I and Q interface
I
4 Input Auxiliary ADC
I
Synthesisers
GP80
Figure 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Voltage applied to any other pin
Operating junction temperature
Storage temperature
ESD (human body model)
-0.3 to 3.9V
-0.3 to Vcc+0.3V
150
°
C
-55
°
C to 150
°
C
2kV
ORDERING INFORMATION
PLUTO/KG/GP1R
APPLICATIONS
I
Dual Mode CDMA/AMPs digital cellular
telephones
Figure 2 Block diagram
PLUTO
Dual Mode CDMA/AMPS Baseband Interface
Advance Information
DS4722 - 1.8 July 1998
PIN 80
PIN 1 IDENT
PIN 1
RX
SYNTH
/4
1025
512
19.68MHz
BUFFER
8-BIT
DAC
8-BIT
DAC
tx calibration and control
TX
SYNTH
8-BIT
DAC
8-BIT
DAC
8-BIT
ADC
6-BIT
ADC
8-BIT
DAC
6-BIT
ADC
8-BIT
ADC
8-BIT
ADC
ANALOG
MULTIPLEXER
rx calibration and control
FM_MOD
TXQ,TXQ-
TXI,TXI-
TXIF
PD_TX
RXIF
PD_RX
FC_I
I+,I-
BAL
Q+,Q-
FC_Q
ADC<3>
ADC<2>
ADC<1>
ADC<0>
S<0>
S<1>
VDD
GND
SUB
FM/
SLEEP/
IDLE/
RESET/
ADCENA
ADCCLK
ADCDATA
RXQD<3:0>
RXID<3:0>
RXQFMDATA
RXIFMDATA
TXD<7:0>
TXCLK
TCXO
CHIPx8
TCXO/4
SDATA
SCLOCK
SLATCH
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