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參數(shù)資料
| 型號(hào)： | KE5BCCA1M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Classification CAM |
| 中文描述： | 分類鈣 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大小： | 105K |
| 代理商： | KE5BCCA1M |
K E 5BCCA1M Classific ation CAM
Kawasaki LSI USA, Inc. www.klsi.com
Silicon Valley Office:
2570 North First Street, Suite 301
San Jose, CA 95131
Tel: (408) 570-0555
Fax: (408) 570-0567 Fax: (781) 224-2501
Kawasaki LSI assumes no responsibility of liability for (1) any errors or inaccuracies contained in the information herein and (2) the
use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b)
direct, indirect, special, or consequential damages. There are no warranties extended or granted by this document. The information
herein is subject to change without notice from Kawasaki LSI.
Eastern Office:
501 Edgewater Dr., Suite 510
Wakefield, MA 01880
Tel: (781) 224-4201
V1.1
Kawasaki LSI’s Classification CAM has a
capacity of 1Mbit (Ternary) and 2 Mbit (Binary),
and can be configured by bank in a mixture of
binary and ternary modes. Its primary application is
in search and filtering. Its flexibility, high speed,
and high capacity make it appropriate for all Layer
2/3/4 and above applications such as switches and
routers in 10/100/1000 Ethernet, Terabit Ethernet
,OC-3/12/48/192, T1/T3, frame relay, ATM, xDSL
and DWDM.
This Classification CAM is also suitable for QoS
applications with its unique and patent-pending
“Auto Shift” commands.
The search time is 15ns and the KE5BCCA1M is
available in a 324-pin BGA.
FEATURES:
High density: 2Mbits Binary, 1Mbit for Ternary
Organization: Configurable table width;
binary/ternary selected by bank
Binary case: 68-bit x 32k, 136-bit x 16k, 272-bit x 8k
Ternary case: 68-bit x 16k, 136-bit x 8k, 272-bit x 4k
High Speed Search :15n sec (1 phase clock)
Latency: 30n sec (2 clock cycles)
Dual-Port Architecture: 68-bit I/O port with
64-bit data bus (optional 32-bit configuration)
Optional 4 extra bits on the data bus
32-bit output port
Cascadable up to 32 pieces
1.
2.
3.
Support for automatic data shifting
Continuous search during data shifting.
Multi-hit support (highest hit address output)
18 Global MASK Registers (68-bit width) for
data search/writing operation.
Automatic learning
Automatic storing of miss-hit data and time
stamp of hit data
Synchronous operation
Clock rate: 66MHz (phase clock)/133MHz
(operating clock) for synchronous operation
324-pin BGA packaging
2.5V/3.3V power supply
I/O
Port
Control
Pipeline
Execution
Control
DAT<63:0>
OEDATN
DATWDT
RSTN
CLK
CNTL<18:0>
RWN
CEN
CSTN
EDAT<3:0>
PHASE
EXTONN
SAD
EAD
Control and Status
Register
Mask Registers
Search Logic
Control Logic
136 bits x 8192
CAM
136 bits x 8192
Local Mask
P
E
D
PHIDN
PHODN
PMIN
PMON
FLIN
FLON
SHON
SMON
PHIUN
PHOUN
F
OEODN
OD<31:0>
O
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