11 FN7693.2 May 2, 2011 Switching Specifications Boldface limits apply over the operating temp" />
參數(shù)資料
型號(hào): KAD5510P-21Q48
廠商: Intersil
文件頁(yè)數(shù): 3/31頁(yè)
文件大小: 0K
描述: IC ADC 10BIT CMOS 210MSPS 48QFN
標(biāo)準(zhǔn)包裝: 50
系列: FemtoCharge™
位數(shù): 10
采樣率(每秒): 210M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 242mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN(7x7)
包裝: 托盤
輸入數(shù)目和類型: *
KAD5510P
11
FN7693.2
May 2, 2011
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITION
SYMBOL
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
ADC OUTPUT
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
Output Clock to Data Propagation Delay,
LVDS Mode (Note 10)
DDR Rising Edge
tDC
-260
-50
120
ps
DDR Falling Edge
tDC
-160
10
230
ps
SDR Falling Edge
tDC
-260
-40
230
ps
Output Clock to Data Propagation Delay,
CMOS Mode (Note 10)
DDR Rising Edge
tDC
-220
-10
200
ps
DDR Falling Edge
tDC
-310
-90
110
ps
SDR Falling Edge
tDC
-310
-50
200
ps
Latency (Pipeline Delay)
L
7.5
cycles
Overvoltage Recovery
tOVR
1cycles
SPI INTERFACE (Notes 11, 12)
SCLK Period
Write Operation
t
CLK
16
cycles
(Note 11)
Read Operation
tCLK
66
cycles
SCLK Duty Cycle (tHI/tCLK or tLO/tCLK)
Read or Write
25
50
75
%
CSB
↓ to SCLK↑ Setup Time
Read or Write
tS
1
cycles
CSB
↑ after SCLK↑ Hold Time
Read or Write
tH
3
cycles
Data Valid to SCLK
↑ Setup Time
Write
tDSW
1
cycles
Data Valid after SCLK
↑ Hold Time
Write
tDHW
3
cycles
Data Valid after SCLK
↓ Time
Read
tDVR
16.5
cycles
Data Invalid after SCLK
↑ Time
Read
tDHR
3
cycles
Sleep Mode CSB
↓ to SCLK↑ Setup Time
(Note 13)
Read or Write in Sleep Mode
tS
150
s
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
applications. Contact factory for more info if needed.
11. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps).
12. The SPI may operate asynchronously with respect to the ADC sample clock but the ADC sample clock must be active to access SPI registers.
13. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time
(4ns min).
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