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參數(shù)資料
| 型號： | KAD5510P-17Q48 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT CMOS 170MSPS 48QFN |
| 標(biāo)準(zhǔn)包裝： | 70 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 220mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
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KAD5510P
23
FN7693.2
May 2, 2011
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation or sleep
modes (refer to “Nap/Sleep” on page 18). This functionality can
be overridden and controlled through the SPI. This is an indexed
function when controlled from the SPI, but a global function
when driven from the pin. This register is not changed by a Soft
Reset.
Nap mode must be entered by executing the following sequence:
Return to Normal operation as follows:
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases. This is
particularly important when multiple ADCs are used in a time-
interleaved system. The phase slip feature allows the rising edge
of the divided clock to be advanced by one input clock cycle when
in CLK/4 mode, as shown in Figure 40. Execution of a phase_slip
command is accomplished by first writing a ‘0’ to bit 0 at address
71h followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles).
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5510P has a selectable clock divider that can be set to
divide by four, two or one (no division, refer to “Clock Input” on
page 17). This functionality can be controlled through the SPI, as
shown in Table 8. This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The KAD5510P can
present output data in two physical formats: LVDS or LVCMOS.
Additionally, the drive strength in LVDS mode can be set high
(3mA) or low (2mA). This functionality can be controlled through
the SPI, as shown in Table 9.
Data can be coded in three possible formats: two’s complement, Gray
code or offset binary. This functionality can be controlled through the
SPI, as shown in Table 10.
This register is not changed by a Soft Reset.
TABLE 6. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
TABLE 7. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER-DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
SEQUENCE
REGISTER
VALUE
1
0x10
0x01
2
0x25
0x02
3
0x10
0x02
4
0x25
0x02
SEQUENCE
REGISTER
VALUE
1
0x10
0x01
2
0x25
0x01
3
0x10
0x02
4
0x25
0x01
TABLE 8. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
TABLE 9. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 10. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
FIGURE 40. PHASE SLIP: CLK
÷4 MODE, fCLOCK = 1000MHz
CLK
CLK÷4
SLIP ONCE
CLK = CLKP – CLKN
CLK÷4
SLIP TWICE
1.00ns
4.00ns
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