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參數(shù)資料
| 型號： | KAD2708C-17Q68 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 170MSPS SGL 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 224mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
13
FN6812.1
April 14, 2011
A back-to-back transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the
termination resistor should be determined based on the
desired impedance.
The sample and hold circuit design uses a switched
capacitor input stage, which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This creates a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier can be used in applications that
require DC coupling, at the expense of reduced dynamic
performance. In this configuration the amplifier will typically
reduce the achievable SNR and distortion performance. A
typical differential amplifier configuration is shown in
Figure 25.
Clock Input
The clock input circuit is a differential pair (see Figure 29).
Driving these inputs with a high level (up to 1.8VPP on each
input) sine or square wave will provide the lowest jitter
performance. The recommended drive circuit is shown in
Figure 26. The clock can be driven single-ended, but this will
reduce the edge rate and may impact SNR performance.
Use of the clock divider is optional. The KAD2708C's ADC
requires a clock with 50% duty cycle for optimum
performance. If such a clock is not available, one option is to
generate twice the desired sampling rate, then use the
KAD2708C's divide-by-2 to generate a 50%-duty-cycle
clock. This frequency divider uses the rising edge of the
clock, so 50% clock duty cycle is assured. Table 2 describes
the CLKDIV connection.
CLKDIV is internally pulled low, so a pull-up resistor or logic
driver must be connected for undivided clock.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter and maximum SNR is shown in
Where tJ is the RMS uncertainty in the sampling instant.
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
differential nonlinearity, aperture jitter and thermal noise.
FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION
ADT1-1WT
0.1F
KAD2708
VCM
50
O
0.01F
Analog
In
ADT1-1WT
Ω
ADTL1-12
0.1F
KAD2708
VCM
ADTL1-12
1nF
Analog
Input
25
O
25
O
FIGURE 24. TRANSFORMER INPUT, HIGH IF APPLICATION
Ω
KAD2708
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
151O
25O
+
Vin
-
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
Ω
TABLE 2. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
AVDD
1
TC4-1W
1nF
AVDD2
200O
CLKP
CLKN
1kO
1nF
Clock
Input
FIGURE 26. RECOMMENDED CLOCK DRIVE
Ω
SNR
20 log10
1
2
πf
INtJ
--------------------
=
(EQ. 1)
KAD2708C
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