- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374297 > K9F2816Q0C-HIB0 (SAMSUNG SEMICONDUCTOR CO. LTD.) INTERNAL SNGL-DRV LOOP CABLE C PDF資料下載
參數(shù)資料
| 型號： | K9F2816Q0C-HIB0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | INTERNAL SNGL-DRV LOOP CABLE C |
| 中文描述： | 1,600 × 8位NAND閃存 |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 583K |
| 代理商： | K9F2816Q0C-HIB0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
K9F2816U0C-DCB0,DIB0
FLASH MEMORY
9
K9F2808U0C-DCB0,DIB0
K9F2808U0C-YCB0,YIB0
K9F2816U0C-YCB0,YIB0
K9F2808U0C-VCB0,VIB0
PRODUCT INTRODUCTION
The K9F28XXX0C is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528(X8 device) or 264(X16 device)
columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8
device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially con-
nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structures. A NAND
structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 1024 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase oper-
ation is prohibited on the K9F28XXX0C.
The K9F28XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9F2816X0C allows sixteen bit wide data
transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows
systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written
through I/O’s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one
bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other com-
mands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for
execution. The 16K-byte(X8 device) or 32K-word(X16 device) physical space requires 24 addresses, thereby requiring three cycles
for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program
need the same three address cycles following the required command input. In Block Erase operation, however, only the two row
address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines
the specific commands of the K9F28XXX0C.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
NOTE
: 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on 2nd half of register by the 01h command, start pointer is automatically moved to
1st half register(00h) on the next cycle.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h/01h
(1)
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
O
Caution
: Any undefined command inputs are prohibited except for above command set of Table 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K9F2816U0C-PIB0 | 16M x 8 Bit NAND Flash Memory |
| K9F2816U0C-HCB0 | 16M x 8 Bit NAND Flash Memory |
| K9F3208W0A- | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; Number of Contacts:128; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle |
| K9F3208W0A-TCB0 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; Number of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| K9F3208W0A-TIB0 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K9F2816U0C-DCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 8 Bit , 8M x 16 Bit NAND Flash Memory |
| K9F2816U0C-DIB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 8 Bit , 8M x 16 Bit NAND Flash Memory |
| K9F2816U0C-HCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 8 Bit NAND Flash Memory |
| K9F2816U0C-HIB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 8 Bit NAND Flash Memory |
| K9F2816U0C-PCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 8 Bit NAND Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。