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    參數(shù)資料
    型號(hào): K9F1G08Q0M-PIB0
    廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
    英文描述: DBM25PK
    中文描述: 1Gb的NAND閃存千兆1.8V的勘誤表
    文件頁(yè)數(shù): 35/38頁(yè)
    文件大?。?/td> 713K
    代理商: K9F1G08Q0M-PIB0
    FLASH MEMORY
    34
    SAMSUNG
    K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
    K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
    K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
    Figure 14. Read ID Operation
    CE
    CLE
    I/O
    X
    ALE
    RE
    WE
    90h
    00h
    Address. 1cycle
    Maker code
    Device code
    t
    CEA
    t
    AR
    t
    REA
    Read ID
    The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
    00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The
    command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
    Device
    Code*
    XXh
    4th Cyc.*
    ECh
    Figure 15. RESET Operation
    RESET
    The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
    read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
    longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
    the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. The R/B pin
    transitions to low for tRST after the Reset command is written. Refer to Figure 15 below.
    FFh
    I/O
    X
    R/B
    t
    RST
    t
    WHR
    t
    CLR
    Device
    Device Code*(2nd Cycle)
    4th Cycle*
    K9F1G08Q0M
    A1h
    15h
    K9F1G08U0M
    F1h
    15h
    K9F1G16Q0M
    B1h
    55h
    K9F1G16U0M
    C1h
    55h
    After Power-up
    After Reset
    PRE status
    High
    Low
    Waiting for next command
    Operation Mode
    First page data access is ready
    00h command is latched
    Table3. Device Status
    相關(guān)PDF資料
    PDF描述
    K9F1G16Q0M-PIB0 DSUB
    K9F1G08U0M 1Gb Gb 1.8V NAND Flash Errata
    K9F1G08U0M-FCB0 1Gb Gb 1.8V NAND Flash Errata
    K9F1G08U0M-FIB0 1Gb Gb 1.8V NAND Flash Errata
    K9F1G08U0M-PCB0 1Gb Gb 1.8V NAND Flash Errata
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    K9F1G08Q0M-YCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb Gb 1.8V NAND Flash Errata
    K9F1G08Q0M-YIB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb Gb 1.8V NAND Flash Errata
    K9F1G08R0A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128M x 8 Bit / 256M x 8 Bit NAND Flash Memory
    K9F1G08R0B-JIB0000 制造商:Samsung SDI 功能描述:PN may be NE SE
    K9F1G08U0A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128M x 8 Bit / 256M x 8 Bit NAND Flash Memory