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參數(shù)資料
| 型號(hào)： | K7B203625A-TC800 |
| 元件分類： | SRAM |
| 英文描述： | 64K X 36 CACHE SRAM, 8 ns, PQFP100 |
| 封裝： | 20 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 438K |
| 代理商： | K7B203625A-TC800 |
K7B203625A
64Kx36 Synchronous SRAM
- 7 -
Rev 3.0
December 1998
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70
°C, VDD=3.3V+0.3V/-0.165V)
* VIL(Min)=-2.0(Pulse Width
≤ tCYC/2)
** VIH(Max)=4.6(Pulse Width
≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
Input Leakage Current(except ZZ)
IIL
VDD=Max , VIN=VSS to VDD
-2
+2
A
Output Leakage Current
IOL
Output Disabled, VOUT=VSS to VDDQ
-2
+2
A
Operating Current
ICC
Device Selected, IOUT=0mA,
ZZ
≤VIL, All Inputs=VIL or VIH
Cycle Time
≥ tCYC min
-75
-
250
mA
-80
-
230
-90
-
200
Standby Current
ISB
Device deselected, IOUT=0mA,
ZZ
≤VIL, f=Max,
All Inputs
≤0.2V or ≥ VDD-0.2V
-75
-
70
mA
-80
-
60
-90
-
50
ISB1
Device deselected,IOUT=0mA, ZZ
≤0.2V,
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
-
20
mA
ISB2
Device deselected, IOUT=0mA, ZZ
≥VDD-0.2V,
f=Max, All Inputs
≤VIL or ≥VIH
-
20
mA
Output Low Voltage(3.3V I/O)
VOL
IOL = 8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
VOH
IOH = -4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
VOL
IOL = 1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
VOH
IOH = -1.0mA
2.0
-
V
Input Low Voltage(3.3V I/O)
VIL
-0.5*
0.8
V
Input High Voltage(3.3V I/O)
VIH
2.0
VDD+0.5**
V
Input Low Voltage(2.5V I/O)
VIL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
VIH
1.7
VDD+0.5**
V
TEST CONDITIONS
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
1ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
1ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,V=2.5V+0.4V/-0.125V, TA=0 to 70
°C)
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