參數(shù)資料
型號(hào): K6X1008C2D-PB70
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
元件分類: DRAM
英文描述: 128Kx8 bit Low Power CMOS Static RAM
中文描述: 128Kx8位低功耗CMOS靜態(tài)RAM
文件頁(yè)數(shù): 6/10頁(yè)
文件大小: 176K
代理商: K6X1008C2D-PB70
CMOS SRAM
K6X1008C2D Family
Revision 1.0
September 2003
6
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS1=OE=V
IL
, CS2=WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data ou
t
NOTES (
READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
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