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參數(shù)資料
| 型號： | K6R4008V1B-I12 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CMOS SRAM |
| 中文描述： | CMOS SRAM的 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 214K |
| 代理商： | K6R4008V1B-I12 |
K6R4008V1B-C/B-L, K6R4008V1B-I/B-P
CMOS SRAM
PRELIMINARY
Rev 2.2
May 1999
- 8 -
NOTES
(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. t
WP
is measured from the beginning of write to the end of
write.
3. t
CW
is measured from the later of CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
* X means Don
′
t Care.
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
I
SB
, I
SB1
L
H
H
Output Disable
High-Z
I
CC
L
H
L
Read
D
OUT
I
CC
L
L
X
Write
D
IN
I
CC
DATA RETENTION CHARACTERISTICS*
(T
A
=0 to 70
°
C)
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
V
CC
for Data Retention
V
DR
CS
≥
V
CC
- 0.2V
V
CC
=3.0V, CS
≥
V
CC
- 0.2V
V
IN
≥
V
CC
- 0.2V or V
IN
≤
0.2V
2.0
-
3.6
V
Data Retention Current
I
DR
-
-
1.0
mA
V
CC
= 2.0V, CS
≥
V
CC
- 0.2V
V
IN
≥
V
CC
- 0.2V or V
IN
≤
0.2V
-
-
0.7
mA
Data Retention Set-Up Time
t
SDR
See Data Retention
Wave form(below)
0
-
-
ns
Recovery Time
t
RDR
5
-
-
ms
DATA RETENTION WAVE FORM
V
CC
3.0V
V
IH
V
DR
CS
GND
Data Retention Mode
CS
≥
V
CC
- 0.2V
t
SDR
t
RDR
CS controlled
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