參數(shù)資料
型號(hào): K6R4004C1C-C10
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1Mx4 Bit High Speed Static RAM(5V Operating).
中文描述: 1Mx4位高速靜態(tài)RAM(5V的工作)。
文件頁數(shù): 2/8頁
文件大小: 155K
代理商: K6R4004C1C-C10
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
CMOS SRAM
PRELIMINARY
Rev 3.0
- 2 -
March 2000
1M x 4 Bit (with OE)High-Speed CMOS Static RAM
GENERAL DESCRIPTION
The K6R4004C1C is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1C uses 4 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG
s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
K6R4004C1C is packaged in a 400 mil 32-pin plastic SOJ.
FEATURES
Fast Access Time 10,12,15,20ns(Max.)
Low Power Dissipation
Standby (TTL) : 60mA(Max.)
(CMOS) : 10mA(Max.)
Operating K6R4004C1C-10 : 160mA(Max.)
K6R4004C1C-12 : 150mA(Max.)
K6R4004C1C-15 : 140mA(Max.)
K6R4004C1C-20 : 130mA(Max.)
Single 5.0V
±
10% Power Supply
TTL Compatible Inputs and Outputs
I/O Compatible with 3.3V Device
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
Standard Pin Configuration
K6R4004C1C-J : 32-SOJ-400
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
19
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O
1
~ I/O
4
Data Inputs/Outputs
V
CC
Power(+5.0V)
V
SS
Ground
N.C
No Connection
system
applications.
The
PIN CONFIGURATION
(Top View)
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
19
A
18
A
17
A
16
A
15
OE
I/O
4
Vss
Vcc
I/O
3
A
14
A
13
A
12
A
11
A
10
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
Vcc
Vss
I/O
2
WE
A
5
A
6
A
7
A
8
A
9
K6R4004C1C-C10/C12/C15/C20
Commercial Temp.
K6R4004C1C-E10/E12/E15/E20
Extended Temp.
K6R4004C1C-I10/I12/I15/I20
Industrial Temp.
ORDERING INFORMATION
Clk Gen.
I/O
1
~I/O
4
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
R
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
1024 Rows
1024 x 4 Columns
I/O Circuit
A
10
A
12
A
14
A
16
A
18
A
11
A
13
A
15
A
17
A
19
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
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