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參數(shù)資料
| 型號(hào)： | K4S64323LH-HC1L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 32Bit x 4 Banks Mobile SDRAM in 90FBGA |
| 中文描述： | 為512k × 32Bit的× 4銀行在90FBGA移動(dòng)SDRAM |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 64K |
| 代理商： | K4S64323LH-HC1L |
K4S64323LF-S(D)N/U/P
Rev. 1.5 Dec 2002
CMOS SDRAM
VDDQ
500
500
Output
30pF
V
OH
(DC) = V
DDQ
-0.2V, I
OH
= -0.1mA
V
OL
(DC) = 0.2V, I
OL
= 0.1mA
Vtt=0.5 x VDDQ
50
Output
30pF
Z0=50
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
AC OPERATING TEST CONDITIONS
(V
DD
= 2.5V
±
0.2V, T
A
= -25
°
C to 85
°
C for Extended, -40
°
C to 85
°
C for Industrial)
Parameter
Value
Unit
AC input levels (Vih/Vil)
0.9 x V
DDQ
/ 0.2
V
Input timing measurement reference level
0.5 x V
DDQ
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
0.5 x V
DDQ
V
Output load condition
See Fig. 2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter
Symbol
Version
Unit
Note
- 75
-1H
-1L
-15
Row active to row active delay
t
RRD
(min)
15
19
19
30
ns
1
RAS to CAS delay
t
RCD
(min)
19
19
24
30
ns
1
Row precharge time
t
RP
(min)
19
19
24
30
ns
1
Row active time
t
RAS
(min)
45
50
60
60
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
65
70
84
90
ns
1
Last data in to row precharge
t
RDL
(min)
2
CLK
2,3
Last data in to Active delay
t
DAL
(min)
tRDL + tRP
-
3
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
4
Number of valid output data
CAS latency=3
2
ea
5
CAS latency=2
1
CAS latency=1
-
0
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