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參數(shù)資料
| 型號(hào)： | K4S510432B-UC75 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mb B-die SDRAM Specification |
| 中文描述： | 512MB的乙芯片內(nèi)存規(guī)格 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 149K |
| 代理商： | K4S510432B-UC75 |
CMOS SDRAM
SDRAM 512Mb B-die (x4, x8, x16)
Rev. 1.1 February 2004
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
4.37
Volts/ns
3
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
1. Rise time specification based on 0pF + 50
to V
SS
, use these values to design to.
2. Fall time specification based on 0pF + 50
to V
DD
, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V
SS
.
Notes :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
75
Unit
Note
Min
7.5
10
Max
CLK cycle time
CAS latency=3
CAS latency=2
t
CC
1000
ns
1
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
ns
1, 2
CAS latency=2
CAS latency=3
6
Output data
hold time
t
OH
3
ns
2
CAS latency=2
3
CLK high pulse width
t
CH
2.5
ns
3
CLK low pulse width
Input setup time
t
CL
t
SS
2.5
1.5
ns
ns
3
3
Input hold time
CLK to output in Low-Z
t
SH
t
SLZ
0.8
1
ns
ns
3
2
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
t
SHZ
5.4
6
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
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