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參數(shù)資料
| 型號： | K4S280432M-TC80 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | K4S280432M-TC80 |
K4S280432M
CMOS SDRAM
Rev. 0.0 Aug. 1999
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
-80
-1H
-1L
-10
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
tCC
8
1000
10
1000
10
1000
10
1000
ns
1
CAS latency=2
12
10
12
13
CLK to valid
output delay
CAS latency=3
tSAC
6
7
ns
1,2
CAS latency=2
6
7
Output data
hold time
CAS latency=3
tOH
3
ns
2
CAS latency=2
3
CLK high pulse width
tCH
3
3.5
ns
3
CLK low pulse width
tCL
3
3.5
ns
3
Input setup time
tSS
2
2.5
ns
3
Input hold time
tSH
1
1.5
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
tSHZ
6
7
ns
CAS latency=2
6
7
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
4.37
Volts/ns
3
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
1. Rise time specification based on 0pF + 50
to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50
to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Notes :
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