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參數資料
| 型號： | K4S161622H-TC80 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16Mb H-die SDRAM Specification |
| 中文描述： | 16Mb的?芯片內存規(guī)格 |
| 文件頁數： | 8/11頁 |
| 文件大小： | 108K |
| 代理商： | K4S161622H-TC80 |
SDRAM 16Mb H-die(x16)
CMOS SDRAM
Rev. 1.5 August 2004
1. Unless otherwise notes, Input level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. K4S161622H-TC
Note :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C )
Parameter
Symbol
Test Condition
Version
Unit
Note
55
60
70
80
Operating Current
(One Bank Active)
I
CC1
Burst Length =1
t
RC
≥
t
RC
(min)
I
o
= 0 mA
120
115
105
95
mA
2
Precharge Standby Current in
power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 10ns
2
mA
I
CC2
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
2
Precharge Standby Current
in non power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during
30ns
15
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
5
Active Standby Current
in power-down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
3
mA
I
CC3
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
3
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during
30ns
25
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
15
mA
Operating Current
(Burst Mode)
I
CC4
I
o
= 0 mA
Page Burst 2Banks Activated
t
CCD
= 2CLKs
155
150
140
130
mA
2
Refresh Current
I
CC5
t
RC
≥
t
RC
(min)
105
100
90
90
mA
3
Self Refresh Current
I
CC6
CKE
≤
0.2V
1
mA
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