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參數(shù)資料
| 型號(hào)： | K4S161622H-TC60 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16Mb H-die SDRAM Specification |
| 中文描述： | 16Mb的?芯片內(nèi)存規(guī)格 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | K4S161622H-TC60 |
SDRAM 16Mb H-die(x16)
CMOS SDRAM
Rev. 1.5 August 2004
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4 / 0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr / tf = 1 / 1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt=1.4V
50
Output
Z0=50
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
30pF
30pF
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
55
60
70
80
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
CC
5.5
1000
6
1000
7
1000
8
1000
ns
1
CAS Latency=2
10
10
10
10
Row active to row active delay
t
RRD(min)
11
-
12
-
14
-
16
-
ns
RAS to CAS delay
t
RCD(min)
16.5
-
18
-
20
-
20
-
ns
Row precharge time
t
RP(min)
16.5
-
18
-
20
-
20
-
ns
Row active time
t
RAS(min)
38.5
-
42
-
49
-
48
-
ns
t
RAS(max)
-
100
-
100
-
100
-
100
us
Row cycle time
t
RC
(
min
)
55
-
60
-
69
-
70
-
ns
Last data in to row precharge
t
RDL(min)
2
1
CLK
2,8
Last data in to new col.address delay
t
CDL(min)
1
CLK
2
Last data in to burst stop
t
BDL(min)
1
CLK
2
Col. address to col. address delay
t
CCD(min)
1
CLK
Mode Register Set cycle time
t
MRS(min)
2
CLK
Number of valid out-
put data
CAS Latency=3
2
ea
4
CAS Latency=2
1
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