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    參數(shù)資料
    型號: K4N51163QC-ZC33
    廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
    英文描述: 512Mbit gDDR2 SDRAM
    中文描述: 512MB的GDDR2 SDRAM的
    文件頁數(shù): 54/64頁
    文件大?。?/td> 1420K
    代理商: K4N51163QC-ZC33
    - 54 -
    Rev 1.5 Oct. 2005
    512M gDDR2 SDRAM
    K4N51163QC-ZC
    If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs
    when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates
    the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-
    down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down
    mode, CKE low and a stable clock signal must be maintained at the inputs of the gDDR2 SDRAM, and ODT should be in
    a valid state but all other input signals are “Don’t Care”. CKE low must be maintained until tCKE has been satisfied.
    Power-down duration is limited by 9 times tREFI of the device.
    The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command).
    CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-
    down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC spec table of
    this data sheet.
    t
    IS
    t
    IS
    CK/CK
    CKE
    Command
    VALID
    NOP
    VALID
    Don’t Care
    NOP
    t
    XP,
    t
    XARD,
    t
    XARDS
    Enter Power-Down mode
    t
    CKE
    t
    IH
    t
    IH
    t
    CKE
    VALID
    t
    IH
    Exit Power-Down mode
    t
    IS
    t
    IH
    t
    CKE
    t
    IH
    VALID
    t
    IS
    V
    IH
    (AC)
    V
    IH
    (DC)
    V
    IL
    (DC)
    V
    IH
    (AC)
    V
    IH
    (DC)
    V
    IL
    (AC)
    V
    IH
    (DC)
    V
    IH
    (AC)
    Basic Power Down Entry and Exit timing diagram
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