參數(shù)資料
型號(hào): K4M563233E-F1L
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
中文描述: 2米x 32Bit的× 4銀行在90FBGA移動(dòng)SDRAM
文件頁(yè)數(shù): 7/12頁(yè)
文件大小: 141K
代理商: K4M563233E-F1L
K4M563233E - M(E)E/N/G/C/L/F
February 2004
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter
Symbol
Version
Unit
Note
-75
-80
-1H
-1L
Row active to row active delay
t
RRD
(min)
15
16
19
19
ns
1
RAS to CAS delay
t
RCD
(min)
19
19
19
24
ns
1
Row precharge time
t
RP
(min)
19
19
19
24
ns
1
Row active time
t
RAS
(min)
45
48
50
60
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
64
67
69
84
ns
1
Last data in to row precharge
t
RDL
(min)
2
CLK
2
Last data in to Active delay
t
DAL
(min)
tRDL + tRP
-
3
Last data in to new col. address
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
4
Number of valid output
CAS latency=3
2
ea
5
Number of valid output
CAS latency=2
1
Number of valid output
CAS latency=1
-
0
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