參數(shù)資料
型號(hào)： K4C89183AF-GIF5
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mb x18 Network-DRAM2 Specification
中文描述： 288Mb x18網(wǎng)絡(luò)DRAM2規(guī)范
文件頁數(shù)： 53/55頁
文件大小： 1470K
代理商： K4C89183AF-GIF5
K4C89183AF
- 53 -
REV. 0.7 Jan. 2005
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
Extended Mode Register Fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled.
(E-2) Output Driver Impedance Control field (A1 to A4)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver
Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.
(E-3) Strobe Select (A6/A5)
Two types of strobe are supported. This field is used to choose the type of data strobe.
(1) Unidirectional DS/QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data at Read operation.
(2) Unidirectional DS/Free running QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data and always clocking
(E-4)Reserved fied (A7 to A14)
These bits are reserved for future operations and must be set to "0" for normal operation.
QS
DQ
Output Driver Impedance Control
A4
0
0
1
1
A3
0
1
0
1
A2
0
0
1
1
A1
0
1
0
1
Normal Output Driver
Strong Output Driver
Weaker Output Driver
Reserved
A6
0
0
1
1
A5
0
1
0
1
Strobe Select
Reserved
Reserved
Unidirectional DS/QS mode
Unidirectional DS/Free running QS mode
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