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| 型號： | K4C89183AF-AIF5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 288Mb x18 Network-DRAM2 Specification |
| 中文描述： | 288Mb x18網(wǎng)絡(luò)DRAM2規(guī)范 |
| 文件頁數(shù)： | 8/55頁 |
| 文件大小： | 1470K |
| 代理商： | K4C89183AF-AIF5 |
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K4C89183AF
- 8 -
REV. 0.7 Jan. 2005
1. All voltages are referenced to Vss, VssQ.
2. V
REF
is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on V
REF
may not exceed ± 2% of V
REF
(DC).
3. Overshoot Iimit : V
IH
(max.) = VddQ + 0.7V with a pulse width <= 5ns
4. Undershoot Iimit : V
IL
(min.) = -0.7V with a pulse width <= 5ns
5. V
IH
(DC) and V
IL
(DC) are levels to maintain the current logic state.
6. V
IH
(AC) and V
IL
(AC) are levels to change to the new logic state.
7. V
ID
is magnitude of the difference between CLK input level and CLK input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. V
ISO
means [V
ICK
(CLK) + V
ICK
(CLK)]/2
10. Refer to the figure below.
Notes
:
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of V
REF
(DC) ± 0.04V.
Pin Capacitance
(V
DD
= 2.5V, V
DDQ
= 1.8V, f = 1 MHz, Ta = 25
o
C
)
Note :
These parameters are periodically sampled and not 100% tested.
Symbol
Parameter
Min
Max
Delts
Units
C
IN
Input Pin Capacitance
1.5
3.0
0.25
pF
C
INC
Clock Pin (CLK, CLK) Capacitance
1.5
3.0
0.25
pF
C
I/O
DQ, DS, QS Capacitance
2.5
3.5
0.5
pF
C
NC
NC Pin Capacitance
-
1.5
-
pF
CLK
CLK
V
SS
V
ID
(AC)
0 V Differential
V
ISO
V
SS
V
ICK
V
ISO
(min)
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ISO
(max)
V
X
V
ID
(AC)
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