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參數(shù)資料
| 型號： | K170 |
| 廠商： | TOKO Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Voltage Operational Amplifier |
| 中文描述： | 低電壓運算放大器 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 44K |
| 代理商： | K170 |
MK1704A
Low EMI Clock Generator
MDS 1704A B
MicroClock Division of ICS 525 Race Street San Jose CA 95126(408)295-9800tel(408)295-9818fax
2
Revision 062599
Printed 11/15/00
ICRO
C
LOC K
Pin #
1
2
3
4
5
6
7
8
Name
ICLK
VDD
GND
CLK
LEE
S1
S0
DC
Type Description
I
Connect to a clock input as shown in the table above.
P
Connect to +3.3V or +5V.
P
Connect to ground.
O
Clock Output; equal to input frequency.
I
Low EMI Enable. Turns on the spread spectrum when high. Internal pull-up.
I
Frequency Select 1 Input. Selects input/output clock range per table above. Internal pull-up.
I
Frequency Select 0 Input. Selects input/output clock range per table above. Internal pull-up.
-
Don't Connect. Do not connect anything to this pin.
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
Pin Assignment
External Components
A minimum number
of external components are required for proper operation. A decoupling capacitor of
0.01μF should be connected between VDD and GND on pins 2 and 3, and a 33
terminating resistor
may be used on the clock output if the trace is longer than 1 inch. The MK1704A is designed for use with a
clock input only. For a crystal input, use the MK1704S or the MK1714-01R.
1
8
2
3
4
7
6
5
ICLK
S0
GND
DC
VDD
LEE
8 pin SOIC
CLK
S1
Clock Output Select Table (in MHz)
*Note: Use only MK1704A with date code of 9909 or later.
Input
Nom
135
80
40
65
Freq. spread
vs. CLK
+0.5, -1.5%
+0.5, -1.5%
Down 2.5%
+0.5, -1.5%
S1
0
0
1
1
S0
0
1
0
1
Min
60
60
30
40
Max Multiplier
140
120
60
100
Mode
*
*
SVGA
XGA
x1
x1
x1
x1
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