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參數(shù)資料
| 型號： | JA58560N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Mask-ROM 8-Bit CMOS Micro-controller |
| 中文描述： | 掩膜ROM的8位CMOS微控制器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 225K |
| 代理商： | JA58560N |
JA58560
Note:
1. The IOST registers are “write-only” and set upon RESET.
2. If the IOST latch is “0”, the corresponding I/O pin is in output mode;
if the IOST latch is “1”, the corresponding I/O pin is in input mode.
RESET
This device may be reset by one of the following ways:
(1) Power-on Reset: At power-up, this device is kept in a RESET condition for a period of 18ms after the
voltage on MCLR pin has reached a logic high level.
(2) MCLR reset (normal operation).
(3) WDT reset (normal operation).
(4) MCLR wake-up (from sleep mode).
(5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device to enter sleep
mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This device can
be awakened by WDT time-out or reset input on MCLR pin.
The contents of registers after reset are listed below:
Address
Register
Power-On Reset
MCLR or WDT Reset
00h
INAR
xxxx xxxx
uuuu uuuu
01h
Timer0
xxxx xxxx
uuuu uuuu
02h
PC
1111 1111
1111 1111
03h
STATUS
0001 1xxx
000# #uuu
04h
FSR
111x xxxx
111u uuuu
05h
PORTA
---- xxxx
---- uuuu
06h
PORTB
xxxx xxxx
uuuu uuuu
07h-1Fh
General Purpose Register
xxxx xxxx
uuuu uuuu
N/A
Acc
xxxx xxxx
uuuu uuuu
N/A
IOST
1111 1111
1111 1111
N/A
T0MODE
--11 1111
--11 1111
Note:
s
x
s
= unknown,
s
u
s
= unchanged,
s
-
s
= unimplemented, read as
s
0
s
,
s
#
s
= refer to the following table
Condition
Status: bit 4
Status: bit 3
MCLR Reset (not during SLEEP)
u
u
MCLR Reset during SLEEP
1
0
WDT Reset (not during SLEEP)
0
1
WDT Reset during SLEEP
0
0
16-10 Ver. 1.1
TEL
Κ
886-3-5770755 FAX
Κ
886-3-5770756 E-mail
Κ
sales@jaztek.com.tw Web-site
Κ
www.jaztek.com.tw
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