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參數(shù)資料
| 型號： | IXDP610PI |
| 廠商： | IXYS |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRL BUS DIGITAL 18-PDIP |
| 標準包裝： | 21 |
| 應用： | PWM 電機控制器 |
| 接口： | 微處理器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 18-DIP |
| 包裝： | 管件 |
| 安裝類型： | 通孔 |
2001 IXYS/DEI All rights reserved
2
IXDP 610
Symbol
Definition
Maximum Ratings
Operating Range
min. max.
V
CC
Supply voltage
4.5
5.5
V
T
A
Operating free air temperature
-40
85
°C
Symbol
Definition/Condition
Characteristic Values
(Over operating range, unless otherwise specified)
min.
typ.
max.
V
IH(CMOS)
Input High Voltage
ODIS
3.8
V
CC +0.3 V
V
IL(CMOS)
Input Low Voltage
ODIS
-0.3
1.2
V
V
H
Input Hysteresis
ODIS
0.3
0.5
V
V
OH
Output High Voltage OUT1 I
OH = -20 mA
2.4
V
OUT2
V
OL
Output Low Voltage OUT1 I
OL = 20 mA
0.4
V
OUT2
V
IH(TTL)
Input High Voltage
All Inputs
2.0
V
CC +0.3 V
Except ODIS
V
IL(TTL)
Input Low Voltage
All Inputs
-0.3
0.8
V
Except ODIS
I
LI
Input Leakage
All Inputs
-10
-0.1
10
A
Current
0 < V
I < VCC
I
CC
Power Supply
f
CLK = 5 MHz
3.5
10 mA
Current
V
IH = VCC or 0
Symbol
Definition/Condition
Characteristic Values
(T
A = 25°C, VCC = 5 V ± 10 %, C1 = 50 pF)
No. see
-40...85
°C
Fig. 3-6
typ.
min. max.
1t
AVWL
SEL Stable to WR Low
5
ns
2t
WHAX
SEL Stable after WR High
10
ns
3t
SLWL
CS Low to WR Low
5
ns
4t
WHSH
CS High after WR High
5
ns
5t
WLWH
WR Pulse Width
8
20
ns
6t
DVWH
Data Valid to WR High
5
ns
7t
WHDX
Data Held after WR High
10
20
ns
8f
CLK
Clock Frequency
50*
050* MHz
9t
CLCH
Clock Pulse Duration Low
12.5
ns
t
CHCL
High
12.5
ns
10 t
CHOV
CLK to Output when
5+T
CLK**
5
5+T
CLK
ns
Writing to PW latch
11 t
ODLOL
ODIS Low to Output Low
20
50
ns
12 t
WHOL
WR High to Output Low
30
60
ns
When Writing Stop to the
Control latch
13 t
RLRH
RST Low Time
50
ns
* Output will change 1 rising CLOCK edge +5ns after WR (see Fig. 6)
** T
clk = 1/fclk
Numbers in the Fig. 3 to 6 corres-
ponding to the time values on the
bottom left of this page.
Fig. 3 Write operation timing diagram
Fig. 4 Output disable to outputs off
timing
Fig. 5 Stop to outputs off timing
Fig. 6 CLOCK to output when writing
to PW latch
OUT 1 or OUT2
WR
OUT1
OUT2
1
8
10
<5ns
9
23
CLK
WR
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