參數(shù)資料
型號: IW4053BN
廠商: Electronic Theatre Controls, Inc.
英文描述: Analog Multiplexer Demultiplexer
中文描述: 模擬多路復用多路解復用器
文件頁數(shù): 1/8頁
文件大?。?/td> 71K
代理商: IW4053BN
TECHNICAL DATA
1
INTEGRAL
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
The IW4053B analog multiplexer/demultiplexer is digitally
controlled analog switches having low ON impedance and very low
OFF leakage current. Control of analog signals up to 20V peak-to-peak
can be achieved by digital signal amplitudes of 4.5 to 20V (if V
CC
- GND
= 3V, a V
CC
- V
EE
of up to 13 V can be controlled; for V
CC
- V
EE
level
differences above 13V a V
CC
- GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full V
CC
-GND and V
CC
- V
EE
supply-voltage ranges,
independent of the logic state of the control signals. When a logic
“1”is present at the ENABLE input terminal all channels are off.
The IW4053B is a triple 2-channel multiplexer having three separate
digital control inputs, A, B, and C, and an enable input. Each control
input selects one of a pair of channels which are connected in a single-
pole double-throw configuration.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1
μ
A at 18 V over full package-temperature
range; 100 nA at 18 V and 25
°
C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
IW4053B
ORDERING INFORMATION
IW4053BN
Plastic DIP
IW4053BD
SOIC
IZ4053B
chip
T
A
= -55
°
to 125
°
C for all packages
PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs
ON
Enable
Select
Channels
C
B
A
L
L
L
L
Z0
Y0
X0
L
L
L
H
Z0
Y0
X1
L
L
H
L
Z0
Y1
X0
L
L
H
H
Z0
Y1
X1
L
H
L
L
Z1
Y0
X0
L
H
L
H
Z1
Y0
X1
L
H
H
L
Z1
Y1
X0
L
H
H
H
Z1
Y1
X1
H
X
X
X
None
H = high level
L = low level
X = don’t care
LOGIC DIAGRAM
Triple Single-Pole, Double-Position
Plus Common Off
PIN 16 =V
CC
PIN 7 = V
EE
PIN 8 = GND
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