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參數(shù)資料
| 型號(hào)： | IT83C154TXXX-30D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 52/238頁(yè) |
| 文件大?。?/td> | 4549K |
| 代理商： | IT83C154TXXX-30D |
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145
8006K–AVR–10/10
ATtiny24/44/84
16.13 Register Description
16.13.1
ADMUX – ADC Multiplexer Selection Register
Bits 7:6 – REFS1, REFS0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 16-3.
If these bits are changed during a conversion, the change will not go in effect until this
conversion is complete (ADIF in ADCSR is set). Also note, that when these bits are changed,
the next conversion will take 25 ADC clock cycles.
Special care should be taken when changing differential channels. Once a differential channel
has been selected the input stage may take a while to stabilize. It is therefore recommended to
force the ADC to perform a long conversion when changing multiplexer or voltage reference set-
tings. This can be done by first turning off the ADC, then changing reference settings and then
turn on the ADC. Alternatively, the first conversion results after changing reference settings
should be discarded.
It is not recommended to use an external AREF higher than (V
CC - 1V) for channels with differ-
ential gain, as this will affect ADC accuracy.
Internal voltage reference options may not be used if an external voltage is being applied to the
AREF pin.
Bits 5:0 – MUX5:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC. In
case of differential input, gain selection is also made with these bits. Selections on Table 16-4 on
page 146 show values for single endid channels and where the differential channels as well as
the offset calibration selections are located. Selecting the single-ended channel ADC8 enables
the temperature measurement. See Table 16-4 on page 146 for details. If these bits are
changed during a conversion, the change will not go into effect until this conversion is complete
(ADIF in ADCSRA is set).
Special care should be taken when changing differential channels. Once a differential channel
has been selected the input stage may take a while to stabilize. It is therefore recommended to
force the ADC to perform a long conversion when changing multiplexer settings. This can be
Bit
765
432
10
REFS1
REFS0
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
ADMUX
Read/Write
R/W
Initial Value
0
Table 16-3.
Voltage Reference Selections for ADC
REFS1
REFS0
Voltage Reference Selection
00
V
CC used as analog reference, disconnected from PA0 (AREF)
0
1
External voltage reference at PA0 (AREF) pin, internal reference turned off
1
0
Internal 1.1V voltage reference
11
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT84B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|400V V(DRM)|8A I(T)RMS|TO-220 |
| IT84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|400V V(DRM)|8A I(T)RMS|TO-220 |
| IT84F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|400V V(DRM)|8A I(T)RMS|TO-220 |
| IT84G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|400V V(DRM)|8A I(T)RMS|TO-220 |
| IT8661F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISA Super I/O Reference Circuit v2.0 | PC Product Line |
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